摘要
在设计基于现场可编程门阵列(FPGA)的时间数字转换器(TDC)时,时钟偏斜等因素产生的气泡误差会造成抽头延迟链(TDL)中的延迟单元失效,导致TDC的分辨率变差。提出了一种防气泡误差编码器,通过统计抽头延迟链中发生变化的抽头个数,该编码器使抽头延迟链跳变顺序按照时间顺序映射,从而消除气泡误差的影响。利用Xilinx Virtex UltraScale+FPGA对该防气泡误差编码器的有效性进行验证,使用该编码器后,基于双端采样法的抽头延迟链TDC分辨率由3.18 ps提升至1.76 ps。实验结果表明,所提出的防气泡误差编码器能够解决气泡误差导致的延迟单元失效的问题,避免分辨率的损失。
The bubble error,caused by clock skewness and other factors,can disable the delay units in the tapped⁃delay line(TDL)and consequently deteriorate the resolution of time⁃to⁃digital converter(TDC),when designing a TDC based on field programmable gate array(FPGA).A bubble error⁃proof encoder was proposed.By counting the number of taps that changed in the TDL,the bubble error⁃proof encoder maps the jump order of the TDL chronologically,thus eliminating the impact of the bubble error.The validity of the bubble error⁃proof encoder was verified using Xilinx Virtex UltraScale+FPGA.By using the bubble error⁃proof encoder,the resolution of the TDC with TDL based on dual⁃sampling method was improved from 3.18 ps to 1.76 ps.The experimental results show that the proposed bubble error⁃proof encoder can solve the problem of delay units invalidity caused by bubble error and avoid the loss of resolution.
作者
陆江镕
李文昌
刘剑
张天一
王彦虎
Lu Jiangrong;Li Wenchang;Liu Jian;Zhang Tianyi;Wang Yanhu(Laboratory of Solid State Optoelectronic Information Technology,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;College of Materials Science and Opto-Electronic Technology,University of Chinese Academy of Sciences,Beijing 100049,China;School of Integrated Circuits,University of Chinese Academy of Sciences,Beijing 100049,China)
出处
《半导体技术》
CAS
北大核心
2024年第5期471-475,482,共6页
Semiconductor Technology
