摘要
提出了一种基于Xilinx Virtex-5FPGA的时间数字转换器。利用Virtex-5中专用进位链CARRY4构造的延迟链,对时钟周期进行内插以得到更高精度的测量。此外,运用布局布线约束来减少延迟链的不一致性,降低了微分非线性（DNL）以及积分非线性（INL）。仿真结果表明,最低有效位（LSB）为52.22ps,精度（RMS）约为25ps,INL为0~0.9LSB,DNL为-0.03~0.1LSB。
The design and implementation of a high resolution time-to-digital converter in a field programmable gate array was proposed.Dedicated carry-in lines in CARRY4 block of the Virtex-5FPGA were utilized for time interpolation,which had realized the fine time measurement within a system clock period.Meanwhile,place and route（PAR）constraints were applied to eliminate the asymmetry of the delay chain,which had resulted in very small integral nonlinearity（INL）and differential nonlinearity（DNL）.The simulation results showed that the RMS time resolution of TDC was about 25 ps,the LSB was 52.22 ps.The INL was 0-0.9LSB,and the DNL was-0.03-0.1LSB.
作者
王巍
周浩
熊拼搏
李双巧
杨皓
杨正琳
袁军
WANG Wei ZHOU Hao XIONG Pinbo LI Shuangqiao YANG Hao YANG Zhenglin YUAN Jun(College of Electronics Engineering~International Semiconductor College, Chongqing University of Posts and Telecommunications, Chongqing 400065, P. R. China)
出处
《微电子学》
CAS
CSCD
北大核心
2016年第6期777-780,787,共5页
Microelectronics
基金
国家自然科学基金资助项目(61404019)
