摘要
基于FPGA芯片Stratix Ⅱ EP2S60F672C4设计实现了数字基带预失真系统中的环路延迟估计模块。该模块运用了一种环路延迟估计新方法,易于FPGA实现。同时,在信号失真的情况下也能给出正确的估计结果。Modelsim SE 6.5c的时序仿真结果和SignalTaps Ⅱ的硬件调试结果验证了模块的有效性。
Based on FPGA chip Stratix II EP2S60F672C, this paper designed and implemented a loop-delay estimation model in predistortion system. This model used a novel method of estimate the loop-delay, which is easy to implement in FPGA, and can give the right loop-delay estimation value under the condition of signal distortion. The timing simulation result of Modelsim SE 6.5c and hardware debugging result of SignalTap Ⅱ verified the valid of the model designed in this paper.
出处
《电子技术应用》
北大核心
2011年第7期29-31,35,共4页
Application of Electronic Technique
