摘要
提出一种基于FPGA的16位数据路径的高级加密标准AES IP核设计方案。该方案采用有限状态机实现,支持密钥扩展、加密和解密。密钥扩展采用非并行密钥扩展,减少了硬件资源的占用。该方案在Cyclone II FPGA芯片EP2C35F484上实现,占用20 070个逻辑单元(少于60%的资源),系统最高时钟达到100 MHz。与传统的128位数据路径设计相比,更方便与处理器进行接口。
This paper presents an architecture for 16-bit datapath Advanced Encryption Standard（AES） IP core based on FPGA.It uses finite state machine,and supports encryption,decryption and key expansion.The round-key is calculated before the beginning of encryption/decryption.It consumes less hardware resources.It is implemented on Cyclone II FPGA EP2C35F484,which consumes 20 070 logic elements,less than 60% of the resources.The IP core can operate at a maximum clock frequency of 100 MHz.Compared with 128-bit datapath AES,it can interface with CPU easily.
出处
《计算机工程》
CAS
CSCD
北大核心
2009年第24期162-164,167,共4页
Computer Engineering
关键词
高级加密标准
IP核
加密
Advanced Encryption Standard（AES）
IP core
encryption
