摘要
高速视频处理系统信号完整性问题主要存在于反射、串扰和延时等三个方面。通过传输线模型分析确定了系统电路板的阻抗特性,根据传输线的特性阻抗与负载阻抗相匹配的原则,提出了采用端接匹配电阻来减少高速总线反射与串扰的方法。在端接电阻前后分别对高速总线部分的信号波形的反射和串扰进行了仿真,而且利用IBIS模型进行了系统的延时分析,结果表明端接电阻的设计方案不仅能够有效减少信号反射和串扰带来的影响,还能够满足系统的时序要求。根据系统信号完整性的仿真结果设计了相应的布线规则,并确定了系统电路板的最终设计方案。布线后仿真和电路板实测结果均可以满足各项信号完整性的要求。
In high-speed video processing system, there are three mainly problems about signal Integrity （SI） in： reflection, crosstalk and delay, the system＇s impedance characteristic was calculated by means of transmission line model analysis. Based on the theory that impedance characteristic of transmission line must match that of load, it was presented what the termination resistant would be used to series in high-speed bus to reduce reflection and crosstalk of high-speed bus. It was simulated that reflection and crosstalk of high-speed bus＇s signal waveform. Based on IBIS model, delay characteristic was analyzed. It turned out that series termination resistant is an effective way to reduce the reflection and crosstalk and satisfies requirement of timing. Next, it is determined that layout rule about SI based on simulation results, and design proposal on layout. Simulation after layout and measured results meet the requirements of SI.
出处
《电子测量与仪器学报》
CSCD
2009年第6期34-41,共8页
Journal of Electronic Measurement and Instrumentation
基金
国家自然科学基金(仪器专项:60627002)资助项目
