摘要
精密的时间作为科研和工程技术等方面的基本物理参量，其测量的基本手段是精密时间一数字转换电路（Time—to-Time Digital Converter，简称TDC）．当前主流的TDC实现方法（“粗”时间测量加”细”时间测量）能达到亚纳秒的时间分辨率，但很难实现一致性很好的精确时间延时，误差较大．基于FPGA具有丰富专用进位连线的资源，对利用现场可编程逻辑器件FPGA中的专用进位连线实现时间内插链，从而实现精密TDC设计，灵活性好，成本低．并对TDC进行了时序仿真，测量的精度可达70ps，取得了一致性很好的精确时间延时．
The accurate time gives an essential parameter to science research and engineering technologies,and it is measwed by using precise time-to-digital converter circuits（TDC）. The main method to realize time-todigital converter circuits（coarse time measurement and fine time measurement ） can achieve subnanosecond time resolution,but it is difficult to realize the precise time delay with good consistency,and the error is great. Because of the dedicated carry line resources of FPGA, the author realizes the time interpolation circuits based on the dedicated carry line of different FPGAs;and then the precise time-to-digital converter circuits（TDC） with high flexity and low cost can be realized. The accuracy of timing simulation of TDC reaches 70 ps,and the precise time delay with good consistency is obtained.
出处
《湘潭大学自然科学学报》
CAS
CSCD
北大核心
2008年第1期51-55,共5页
Natural Science Journal of Xiangtan University
基金
国家自然科学基金资助项目（10647132）资助
