摘要
本文介绍一种利用数字电路 ,设计高可靠冗余时钟的方案。本方案特别设计了毛刺消除电路对信号的毛刺进行滤除 ,同时还设计了针对震荡信号特点的边沿三取二表决电路 ,采用分段TMR结构提高冗余时钟整体可靠性。最后 ,我们还针对选用FPGA的特性作了相对改动 。
This article introduces a high-reliability redundancy clock scheme which is designed by digital circuit. We designed special circuit for the scheme to remove the burr. At the same time, we designed edge TMR-voter circuit for clock signal. The subsection TMR structure improve the clock system reliability on the whole. At last, we make some improvements to fit the FPGA characteristic. This insures the fault-tolerant ability of the scheme.
出处
《电子测量与仪器学报》
CSCD
2004年第1期66-71,共6页
Journal of Electronic Measurement and Instrumentation
