摘要
RISC-V指令集架构定义了支持巨页的多层页表结构,但是由于早期的RISC-V处理器核多定位于嵌入式领域,在内存管理单元(Memory Management Unit,MMU)设计上无法发挥其全部能力,比如页目录缓存和对ASID的支持。本文研究基于RISC-V指令集的高性能MMU设计,采用两级MMU结构:一级MMU分为指令MMU和数据MMU,其中数据MMU支持非阻塞访问,通过增加缺失状态队列,在转译后备缓冲(Translation Lookaside Buffer,TLB)重填后激活保留站中之前因TLB缺失而被挂起的指令;二级MMU采用多级转译缓存结构,通过对页目录的缓存加速TLB加载过程,并支持硬件TLB加载。针对RISC-V指令集定义的TLB无效指令,本文利用组相联cache的结构特点,将无效过程分为组无效和重填时进行路无效这两个阶段,实现了快速的全局无效和按AISD无效TLB的操作。经过验证,MMU可以在28 nm工艺下稳定运行在1.2 GHz,采用多级转移缓存保存页目录的设计使得MMU的访存请求减少了66.65%,TLB加载的平均执行周期减少了65.54%。
RISC-V instruction set architecture defines a multi-level page table structure that supports huge pages.However,because the early RISC-V processor cores are mostly focus on the embedded field,the full capabilities of RISC-V instruction set,such as page directory caching and ASID are not fully exploited in their Memory Management Unit(MMU)design.This paper studies the design of high-performance MMU based on RISC-V instruction set.A two-level MMU design is adopted.The first-level MMU is divided into instruction MMU and data MMU.The data MMU supports nonblocking access by adding a missing state queue,the instructions suspended in the reserved station due to Translation lookaside Buffer(TLB)missing are activated after TLB refill.The second-level MMU adopts a multi-level translation cache structure,which accelerates the TLB loading process by caching the page directory and supports hardware pagetable walk.For the invalid instructions of TLB defined by RISC-V instruction set,this paper uses the structure characteristics of group associated cache to divide the invalid process into two stages:group invalid and way invalid when refilled,to achives the fast global invalid and AISD invalid TLB operation.It is verified that the MMU can run stably at 1.2 GHz under 28 nm process.The design of multi-level translation cache to save the page directory reduces the memory access requests of MMU by 66.65%,and the average execution cycle of TLB loading is reduced by 65.54%.
作者
杨思博
于敦山
YANG Sibo;YU Dunshan(School of Software&Microelectronics,Peking University,Beijing 102600,China)
出处
《微电子学与计算机》
2025年第2期93-102,共10页
Microelectronics & Computer
关键词
页表
页目录
内存管理单元
转译后备缓冲(TLB)
page table
page directory
memory management unit(MMU)
translation lookaside buffer(TLB)
