摘要
为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的容忍能力,可以带来ADC性能上的提升。系统采用上极板采样,可以在采样周期结束的瞬间就开始逐位比较过程,省去了采用底极板采样第一拍CDAC建立的过程,提高了转换速度,相对于底极板采样也节省了一定的开关功耗。后仿结果表明,模拟输入20 kHz差分中频信号,在500 kHz采样频率,3.3 V电源电压下,ADC的有效位数为11.56 bit,SNR为71.04 dB,SFDR为80.37 dBc,功耗约为2 mW。
To meet the needs of 5.8 GHz radar system,a 12bit SAR ADC is designed in HLMC55LP process,the sampling rate of ADC is adjustable in two steps of 500 kHz/250 kHz,single-tuned capacitor switching timing is used,and 2 redundant bits are added to the high part of the capacitor array design,the redundant bits have certain tolerance to the high CDAC establishment error,comparator error The redundant bits are tolerant to the high CDAC establishment error and comparator error,which can bring about an improvement in ADC performance.The system uses the upper pole plate sampling,which can start the bit-by-bit comparison process at the end of the sampling period,eliminating the need to use the bottom plate sampling for the first CDAC build process and increasing the conversion speed,as well as saving some switching power compared to the bottom plate sampling.The post-imitation results show that the ADC has an effective bit count of 11.56 bit,SNR of 71.04 dB,SFDR of 80.37 dBc,and power consumption of about 2 mW at 500 kHz sampling frequency and 3.3 V supply voltage for a 20 kHz differential IF signal.
作者
郑喜鹏
陈磊
伍振环
邢蕾
ZHENG Xipeng;CHEN Lei;WU Zhenhuan;XING Lei(College of Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 201306,China)
出处
《电子设计工程》
2024年第13期93-98,共6页
Electronic Design Engineering
关键词
逐次逼近型模数转换器
上极板采样
冗余结构
单调电容开关时序
successive approximation analog-to-digital converter
upper plate sampling
redundant structure
monotonic capacitive switching timing
