摘要
并行计算是提高系统资源利用率的重要手段,越来越多的多处理器片上系统通过集成具有不同功能特点的处理器来满足不同计算任务的需求。具备动态部分可重构特性的异构多处理器片上系统(Dynamic Partial Reconfiguration-Heteroge-neous Multiprocessor Systems-on-Chip, DPR-HMPSoC)因其并行性好、计算效率高而被广泛使用,而低复杂度和高求解性能的软硬件划分算法是充分发挥其计算性能优势的重要保证。已有的相关软硬件划分算法时间复杂度高,且对DPR-HMPSoC平台的支撑不足。针对上述问题,首先提出了一种列表启发式软硬件划分与调度算法,其通过构建基于任务优先级的调度列表,完成任务的调度、映射、FPGA动态部分可重构区域划分等一系列操作;接着给出了软件应用建模、计算平台建模及所提算法的详细设计方案。仿真实验结果表明,所提算法与混合整数线性规划(Mixed Integral Linear Programming, MILP)和蚁群优化(Ant Colony Optimization, ACO)算法相比,可有效减少求解时间,且时间优势与任务规模成正比;在调度长度方面,所提算法的平均性能提升了约10%。
Parallel computing is an important means to improve the utilization rate of system resources.More and more systems on multi-processor chip meet the requirements of different computing tasks by integrating processors with different functional characteristics.A heterogeneous multiprocessor system-on-chip(DPR-HMPSoC)with dynamic partial reconfigurability is widely used because of its good parallelism and high computing efficiency,while the software/hardware partitioning algorithm with low complexity and high solving performance is an important guarantee for giving full play to its computational performance advantages.The existing related software/hardware partitioning algorithms have high time complexity and insufficient support for the DPR-HMPSoC platform.In response to the above problems,this paper proposes a list heuristic software/hardware partitioning and scheduling algorithm.By constructing a scheduling list based on task priority,a series of operations such as task scheduling,mapping and FPGA dynamic partial reconfigurable area partitioning are completed.It introduces software application mode-ling,computing platform modeling,and the detailed design scheme of the proposed algorithm.The simulation experiment results show that the proposed algorithm can effectively reduce the solution time compared with the MILP and ACO algorithms,and the time advantage is proportional to the task scale.In terms of scheduling length,the average performance of the proposed algorithm is improved by about 10%.
作者
郭彪
唐麒
文智敏
傅娟
王玲
魏急波
GUO Biao;TANG Qi;WEN Zhi-min;FU Juan;WANG Ling;WEI Ji-bo(College of Electrical and Information Engineering,Hunan University,Changsha 410082,China;School of Electronic Science and Technology,National University of Defense Technology,Changsha 410073,China;Vehicle Department of Changsha Rail Transit Operation Co.,Ltd,Changsha 410000,China;Institute of System Engineering,Academy of Chinese PLA Military Science,Beijing 100101,China)
出处
《计算机科学》
CSCD
北大核心
2021年第6期19-25,共7页
Computer Science
