摘要
基于一款国产FPGA芯片的研发,提出了一种具有高可靠性、高速及可编程性的异步FIFO电路结构。通过增加近空满示警阈值和近空满状态位的方式用以提高异步FIFO的可编程性,同时内部通过使用格雷码指针进行比较的结构用以提高电路的可靠性。并在此基础上,提出了一种新的空满判断标准,使系统速度和逻辑利用率得到了进一步的提升。基于UMC28nm标准CMOS工艺,采用全定制方法进行电路设计。仿真结果表明,提出的异步FIFO在1V的标准电压下,最高工作频率为666.6MHz,平均功耗为7.1mW。
Based on the research of a domestic field programmable gate array(FPGA) chip, an asynchronous first input first output(FIFO) circuit structure with high reliability, high speed and programmability is proposed. By adding the full/empty warning threshold and the full/empty state bit, the programmability of the proposed asynchronous FIFO is improved. Meanwhile, the reliability of the circuit is improved by using the Gray code pointer for comparation. On this basis, a new criterion for judging the full/empty state is proposed, which is applied to further improve the system working speed and logic utilization. Based on the United Microelectronics Corporation(UMC) 28 nm standard complementary metal oxide semiconductor(CMOS) process, the circuit design is carried out by fully customized method. The simulation results show that the proposed asynchronous FIFO has a maximum operating frequency of 666.6 MHz and an average power consumption of 7.1 mW at 1 V standard voltage.
作者
牛博
赵宏亮
Niu Bo;Zhao Hongliang(School of Physics,Liaoning University,Shenyang 110036,China)
出处
《电子技术应用》
2019年第7期36-39,43,共5页
Application of Electronic Technique
基金
辽宁省教育厅研究生教育教学改革联合培养项目(辽教函[2017] 24号)
关键词
可编程性
异步FIFO
近空满示警阈值
格雷码指针
空满判断
programmability
asynchronous FIFO
full/empty warning threshold
Gray code pointer
full/empty judgment
