摘要
为探索三维现场可编程门阵列(FPGA)芯片温度的影响因素,提出一种三维FPGA有限元仿真模型。首先,利用商业有限元软件构建基于硅通孔(TSV)、微凸块、倒装焊共晶焊球、无源硅中介层、焊球阵列(BGA)焊球和印制电路板(PCB)的模型。然后,利用该模型从定性和定量的角度对不同TSV数目及堆叠层数的三维FPGA芯片进行温度分析。实验发现,底层芯片到顶层芯片的平均温度呈递增趋势,且各层芯片的平均温度随TSV数目的减少和堆叠层数的增加而升高。实验结果与已发表文献中的结果一致,表明提出的仿真模型在分析芯片温度的影响参数方面的可行性。
To explore the factors affecting the temperature of the three dimensional Field Programmable Gate Array(FPGA)chip,a finite element simulation model targeted three dimensional FPGA is proposed.First,the model is constructed using commercial software Flotherm based on Through SiliconVia(TSV),micro bump,flip chip eutectic bump,interposer,Ball Grid Array(BGA)solder ball and PCB.Then,the model is adopted to analyze the temperature of the three dimensional FPGA chip with different numbers of TSVs and stacking layers from qualitative and quantitative point of view.It is found that the average temperature increases from the bottom chip to the top chip,and the average temperature of each layer increases with the decrease of the number of TSVs and the increase of the number of stacking layers.The experimental results are consistent with the results published in the literature,indicating the feasibility of the proposed simulation model in the analysis of the parameters influencing the temperature of the chip.
作者
黄俊英
张超
林郁
孙嘉斌
杨海钢
HUANG Junying;ZHANG Chao;LIN Yu;SUN Jiabin;YANG Haigang(System on Programmable Chip Research Department,Institute of Electronics,Chinese Academy of Sciences, Beijing 100190, China;University of Chinese Academy of Sciences,Beijing 100190,China)
出处
《太赫兹科学与电子信息学报》
2017年第2期302-306,共5页
Journal of Terahertz Science and Electronic Information Technology
关键词
三维现场可编程门阵列
有限元模型
硅通孔
堆叠层数
3-D Field Programmable Gate Array
finite element model
Through Silicon Via
stacking layers
