摘要
基于串行/解串器技术的核电子学时钟同步系统的抖动会逐级累积,为此设计了基于锁相环的时钟抖动消除电路。通过选择合适的环路滤波器带宽,可以将时钟抖动降低到9 ps左右。建立了附加抖动模型以估计时钟分发的最大级数。测试表明,时钟抖动消除电路能够保证全局时钟顺利分发下去,可以在实际工程设计中借鉴使用。
In the nuclear electronics clock distribution system based on serializer/deserializer （SerDes）, jitter will gradually accumulate. In order to solve this problem, a clock jitter cleaner cireuit based on phase - locked loop （PLL） is designed. By selecting the appropriate loop filter bandwidth, clock jitter can be reduced to about 9 ps. In order to estimate the maximum series of cloek distribution, a model of additional clock jitter is built. Test results show that the clock jitter cleaner circuit can guarantee the global clock successfully distributed, and can be referenced and used in practieal engineering design.
出处
《核电子学与探测技术》
CAS
北大核心
2016年第6期574-577,共4页
Nuclear Electronics & Detection Technology
基金
国家自然科学基金(41274184)资助
