摘要
随着计算机技术以及微电子技术的迅速发展,测试系统正从单一功能系统向通用系统方向发展。针对多种通用总线,采用最新的基于EAPR的动态局部重构方法,并结合基于FPGA的嵌入式开发流程,设计了一套微处理器加FPGA的动态局部自重构系统。该系统有一个重构区域,可以实现CAN总线、ARINC 429、232和422不同总线的时分复用或某些总线的混合使用。利用Virtex-4上集成的微处理器控制内部配置访问端口ICAP完成不同总线通信模块的动态重构,并在FEM025开发板上进行自重构验证,以小规模硬件逻辑资源实现了大规模系统功能。
With the rapid development of compute technology and micro-electronics technology,the test system is developing from a singal functional system to a universal functional system.For a variety of universal bus,a kind of dynamic partial self-reconfigurable system which is composed of micro-processor and FPGA will be presented in this paper,that combines the newest dynamic partial reconfigurable method based on EAPR and embedded development process based on FPGA.The system has a reconfigurable region in which CAN bus,ARINC 429,232 and 422bus can run alone at different time periods or several buses of these run at the same time.Different communicational bus modules can be reconfigured dynamically by using micro-processor integrated in Virtex-4 to control internal configuration access port ICAP.The result will be verified on FEM025 development board,which indicates that small scale hardware is able to achieve the function of large scale system.
出处
《电子测量技术》
2015年第2期16-19,共4页
Electronic Measurement Technology
关键词
通用总线
EAPR
动态局部重构
内部配置访问端口
universal bus
EAPR
dynamic partial reconfiguration
internal configuration access port
