摘要
描述了一种新型的高性能高能效SIMD乘法阵列的结构.该乘法阵列支持同时执行1个64位乘法,4个32位乘法或16个16位有符号/无符号乘法.通过修改乘法算法实现结构,提高了乘加单元的面积复用度,在较小的面积和性能开销下实现了上述功能.并引入了"溢出补偿技术"解决了复数矩阵乘法运算的判溢出问题.通过牺牲非关键路径上短位宽乘法性能,提高关键路径上高位宽乘法性能.所述结构与文献[1]中乘法簇结构相比,64位乘法延时减少3.65%,面积降低3.92%,功耗提高5.71%.
This paper presents a 64-bit fixed-point SIMD multiplication array .This array has capable of supporting one 64 × 64 ,four 32 ×32 or sixteen 16 × 16 bit signed/unsigned . The component is used more efficient with multiplication cell array .Implement all above function with a small increase in delay and area .An algorithmof“overflow compensate” is introduced ,which solve the overflow judgment in fixed-point complex multiplication .The synthesize result shows that the multiplication reduces the 64 bit multiplication′s critical path by 3 .65% ,reduces the area by 3 .92% and increases the power consumption by 5 .71% .
出处
《微电子学与计算机》
CSCD
北大核心
2014年第3期9-13,共5页
Microelectronics & Computer
基金
国家自然科学基金项目"多核多线程DSP适应性存储结构研究"(61070036)
