摘要
利用FPGA并行技术,采用软实时的嵌入式处理器与高速硬实时的可编程FPGA模块结合方式实现了128路被动模拟信号的高速实时动态生成;系统由一路信号实时产生出具有不同相位和噪声的128路信号;实时系统将一路信号下发后,FPGA通过并行插值运算产生不同通道间的时延,叠加高斯背景噪声信号后经乒乓缓存输出;系统以192kHz输出采样率每333μs更新缓冲区数据,由此输出节拍控制装订参数与实时计算节拍;系统测试结果表明生成128路的模拟信号可编程FPGA工作时钟只需要12M即可保证连续输出,需要系统开辟的输出乒乓缓冲区大小为32K,可保证系统在最高采样速率下实时计算输出被动辐射噪声信号,满足系统实时性要求。
using the embedded soft real time processor combining high speed hard real time module to generate 128 channel simulation signals based on FPGA parallel technology.128 signals which have different time delay and noise is generated by one channel.When parameters loaded by real time system,the different time delay of multi-channels are parallel computed after liner interpolation,by overlapping background noise,the multi channel signal parallel output through pingpang buffer memory.The output buffer update data per 333us,meanwhile,according to this tempo,FPGA start loading parameters and computing.The system test results show that generate 128 simulation signals FPGA working clock just needed 12MHz.Meanwhile,less than 32K system flash memory space is needed to ensure continuous simulation signal output.Experimental results show that System has high real time ability and reliability.
出处
《计算机测量与控制》
CSCD
北大核心
2011年第4期935-937,940,共4页
Computer Measurement &Control
