摘要
介绍了在时序电路设计中应用卡诺图进行逻辑函数化简时的一种简捷方法，按本方法化简设计出的电路可以满足所用触发器和门电路数目最少以及触发器和门电路输入端数目最少的“最简”要求。方法易于掌握，使用方便。
The paper introduces a simple and direct method of simplifying logic function by making use of Karnaugh map in designing sequence circuit. According to the method, the circuits designed may satisfy certain requirements, i.e.the Flip Flop and gate circuits as well as the least fan ins. The method is known easily and is applied conveniently.
出处
《淮海工学院学报（自然科学版）》
CAS
1999年第1期13-16,共4页
Journal of Huaihai Institute of Technology:Natural Sciences Edition
