摘要
CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图、工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应关键技术方案。
Device channel length become more and more short under CMOS Scaling, such that latch - up effect in CMOS structure is stand out increasingly. Latch - up is a parasitic effect in CMOS circuits. Once the parasitic BJT is triggered , there will be high current from UDD to GND,which makes the chip invalidation. Firstly, the mechanism and trigger mode of latch - up effect in CMOS structure are analyzed, as a result, the conditions for the produce of latch - up is obtained. Then these conditions are analyzed, and many means which come from layout or process are considered to prevent latch - up, Finally, the key technologies of the latch -up prevention are given.
出处
《电子工艺技术》
2008年第3期142-145,共4页
Electronics Process Technology
基金
发展基金资助(项目编号:KYTZ200713)
