摘要
信息加密是一种解决网络信息安全问题最直接有效的方法。为了满足大量连续数据加解密的需求,通过对流水结构的优化,对子密钥生成与选通模块的并行设计,开发了一种高速3-DES算法IP核,具有很好的灵活性和适应性,适用于宽带高速网络设备。该IP核采用专用集成电路设计的方法,可用于片上系统的设计,通过仿真可知其最高加解密速率能够达到6.05 Gb/s。
Information encryption is one of the most direct and effective method to resolve the problem of network security. In order to meet the need of encryption or decryption of large quantities of successive data,through optimizing the pipeline and designing the subkey generation module and multiplexers module in parallel,this paper aims at developing a high speed 3 - DES algorithm IP core,which is fit for broad - band network devices of high speed with its flexibility and adaptability. It is designed as ASIC and is easily to be used in SoC design. The simulation shows that the maximum throughputs can get to 6. 05Gbps.
出处
《现代电子技术》
2007年第22期108-110,共3页
Modern Electronics Technique
