摘要
介绍了一种CMOS低压差+5V三端稳压源。在电路设计上,将PMOS管作为调整管,采用带隙基准和NMOS基准两种结构,重点讨论了影响低压差电源的几个因素;在工艺上,采用硅栅自对准CMOS工艺,做出了100mA时压差为0.3V的+5V三端电源。采用NMOS基准的三端稳压源,其静态电流和电源抑制比等参数优于采用带隙基准的三端稳压源。
A lowdropout +5 V threeport linear voltage regulator is presented in the paper With a PMOS transistor as a pass element, the bandgap reference and NMOS reference were designed, respectively It is demonstrated that both of the two references can satisfy the requirement of the linear regulators,but the sample using NMOS reference has a lower quiescent current and a higher voltage rejection ratio than that using bandgap reference The device is fabricated with Sigate selfaligned CMOS process.
出处
《微电子学》
CAS
CSCD
北大核心
2002年第6期462-464,468,共4页
Microelectronics
