The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with...The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.展开更多
A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can mo...A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.展开更多
A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of...A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.展开更多
Activin A, which was first described in 1986, has been shown to maintain hippocampal neuronal survival. Activin A increases intracellular free Ca2＋ via L-type Ca2＋ channels. Our previous study showed that activin A ...Activin A, which was first described in 1986, has been shown to maintain hippocampal neuronal survival. Activin A increases intracellular free Ca2＋ via L-type Ca2＋ channels. Our previous study showed that activin A promotes neurite growth of dorsal root ganglia in embryonic chickens and inhibits nitric oxide secretion. The present study demonstrated for the first time that activin A could maintain cerebral cortex neuronal survival in vitro for a long period, and that activin A was shown to increase voltage-gated Na＋ current （/Na） in Neuro-2a cells, which was recorded by patch clamp technique. The present study revealed a novel mechanism for activin A, as well as the influence of activin A on neurons by regulating expressions of vasoactive intestine peptide and inducible nitric oxide synthase.展开更多
A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFE...A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.展开更多
It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord wi...It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord with the FPE model.Therefore,a modified FPE model is developed in which an additional leakage current,besides the gate(ⅠⅡ),is added.Based on the samples with different passivations,the ⅠⅡcaused by a large number of surface traps is separated from total gate currents,and is found to be linear with respect to(φB-Vg)0.5.Compared with these from the FPE model,the calculated results from the modified model agree well with the Ig-Vgmeasurements at temperatures ranging from 295 K to 475 K.展开更多
This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three ...This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three types of SiN layers with different deposition conditions were deposited on GaN HEMTs. Atomic force microscope（AFM）, capacitance-voltage（C-V）, and Fourier transform infrared（FTIR） measurement were used to analyze the surface morphology, the electrical characterization, and the chemical bonding of SiN thin films, respectively. The better surface morphology was achieved from the device with lower gate leakage current. The fixed positive charge Qf was extracted from C-V curves of Al/SiN/Si structures and quite different density of trap states（in the order of magnitude of 1011-1012 cm^（-2）） was observed.It was found that the least trap states were in accordance with the lowest gate leakage current. Furthermore, the chemical bonds and the %H in Si-H and N-H were figured from FTIR measurement, demonstrating an increase in the density of Qf with the increasing %H in N-H. It reveals that the effect of SiN passivation can be improved in GaN-based HEMTs by modulating %H in Si-H and N-H, thus achieving a better Schottky characteristics.展开更多
This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration o...This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.展开更多
Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explici...Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.展开更多
A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both expone...A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.展开更多
We have analyzed the operating mechanism of the novel deep submicrometer SOI drive-in gate controlled hybrid transistor (DGCHT), which can effectively alleviate the contradiction between speed enhancement and power re...We have analyzed the operating mechanism of the novel deep submicrometer SOI drive-in gate controlled hybrid transistor (DGCHT), which can effectively alleviate the contradiction between speed enhancement and power reduction in conventional MOS devices and can improve the output resistance. On the basis of this, the subthreshold current model of DGCHTs is proposed. The model takes into account the impact of lateral non-uniform doping profile on body effect, short-channel effect and carrier mobility. Considering the mobile charge, two-dimensional Poisson equation is solved with quasi-two-dimensional analysis and parabolic approximation of surface potential. With the surface potential obtained, the subthreshold current is figured out, including both the diffusion and drift component. The calculated results are in good agreement with the MEDICI numerical simulation results, indicating the correct description of the current characteristics of SOI DGCHT by the presented model. The model can also be considered as an important reference to the current simulation of deep submicrometer MOSFET with pocket implantation.展开更多
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics ...A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.展开更多
The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface...The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.展开更多
In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the...In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.展开更多
A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been...A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.展开更多
文摘The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.
文摘A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.
文摘A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.
基金the National Natural Science Foundation of China, No.30903123, 30901329the Project of Science and Technology of Jilin Province, No.20090741, 20090185
文摘Activin A, which was first described in 1986, has been shown to maintain hippocampal neuronal survival. Activin A increases intracellular free Ca2＋ via L-type Ca2＋ channels. Our previous study showed that activin A promotes neurite growth of dorsal root ganglia in embryonic chickens and inhibits nitric oxide secretion. The present study demonstrated for the first time that activin A could maintain cerebral cortex neuronal survival in vitro for a long period, and that activin A was shown to increase voltage-gated Na＋ current （/Na） in Neuro-2a cells, which was recorded by patch clamp technique. The present study revealed a novel mechanism for activin A, as well as the influence of activin A on neurons by regulating expressions of vasoactive intestine peptide and inducible nitric oxide synthase.
文摘A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.
基金supported by the National Natural Science Foundation of China(Grant No.61306113)
文摘It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord with the FPE model.Therefore,a modified FPE model is developed in which an additional leakage current,besides the gate(ⅠⅡ),is added.Based on the samples with different passivations,the ⅠⅡcaused by a large number of surface traps is separated from total gate currents,and is found to be linear with respect to(φB-Vg)0.5.Compared with these from the FPE model,the calculated results from the modified model agree well with the Ig-Vgmeasurements at temperatures ranging from 295 K to 475 K.
文摘This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three types of SiN layers with different deposition conditions were deposited on GaN HEMTs. Atomic force microscope（AFM）, capacitance-voltage（C-V）, and Fourier transform infrared（FTIR） measurement were used to analyze the surface morphology, the electrical characterization, and the chemical bonding of SiN thin films, respectively. The better surface morphology was achieved from the device with lower gate leakage current. The fixed positive charge Qf was extracted from C-V curves of Al/SiN/Si structures and quite different density of trap states（in the order of magnitude of 1011-1012 cm^（-2）） was observed.It was found that the least trap states were in accordance with the lowest gate leakage current. Furthermore, the chemical bonds and the %H in Si-H and N-H were figured from FTIR measurement, demonstrating an increase in the density of Qf with the increasing %H in N-H. It reveals that the effect of SiN passivation can be improved in GaN-based HEMTs by modulating %H in Si-H and N-H, thus achieving a better Schottky characteristics.
基金Sponsored by Motorola CPTL(Contract No:MSPSDDLCHINA-0004)
文摘This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.
基金This work was supported by the National Natural Science Foundation of China (No60472003)
文摘Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.
基金Project supported by the National Natural Science Foundation of China(No.61204100)the Guangdong Natural Science Foundation(No.S2013010013088)
文摘A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.
文摘We have analyzed the operating mechanism of the novel deep submicrometer SOI drive-in gate controlled hybrid transistor (DGCHT), which can effectively alleviate the contradiction between speed enhancement and power reduction in conventional MOS devices and can improve the output resistance. On the basis of this, the subthreshold current model of DGCHTs is proposed. The model takes into account the impact of lateral non-uniform doping profile on body effect, short-channel effect and carrier mobility. Considering the mobile charge, two-dimensional Poisson equation is solved with quasi-two-dimensional analysis and parabolic approximation of surface potential. With the surface potential obtained, the subthreshold current is figured out, including both the diffusion and drift component. The calculated results are in good agreement with the MEDICI numerical simulation results, indicating the correct description of the current characteristics of SOI DGCHT by the presented model. The model can also be considered as an important reference to the current simulation of deep submicrometer MOSFET with pocket implantation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61306116 and 61472322)
文摘A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376099,11235008,and 61205003)
文摘The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.
基金supported by the National High Technology Research and Development Program of China(Grant No.2015AA016501)the National Natural Science Foundation of China(Grant No.61306129)
文摘In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.
基金supported by the 2010 School Fundamental Scientific Research Fund of Xidian University (Grant No. K50510250008)
文摘A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.
