The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band an...The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.展开更多
A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is propose...A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver（RX）with an ultra-low-power free-running ring oscillator and a high speed main transmitter（TX）with fast lock-in PLL.A passive wake-up receiver（WuRx）for wake-up function with a high power conversion efficiency（PCE）CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm^2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves ＋3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.展开更多
This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx...This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx） cores and a dual-carrier frequency synthesizer（DC-FS） as well as a 3-wire serial peripheral interface（SPI） to set the operating status of the transceiver.The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 x 3.6 mm2.The measurement results show that the wideband Rx achieves an NF of 5-6.2 dB,a max gain of 76-84 dB with 64-dB variable gain,an in-/out-of-band IIP3 of-6/＋4 dBm and an input loss S11 of〈-10 in all bands.The Tx achieves an LOLRR/IMGRR of-34/-33 dBc,a typical OIP3 of＋6 dBm and a maximum output power of -5 dBm.The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of〈1.2 ns.The full chip consumes a maximum current of 420 mA under a 1.2-V supply.展开更多
This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth...This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.展开更多
A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two t...A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
This paper presents a 5 GHz CMOS radio frequency （RF） transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple- in multiple-o...This paper presents a 5 GHz CMOS radio frequency （RF） transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple- in multiple-out （MIMO） technology with other wireless technologies to provide high data rate robust real-time high definition television （HDTV） distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz： the industrial, scientific and medical （1SM） band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude （EVM） at -3 dBm output power.展开更多
This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-set...This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.展开更多
基金The National Natural Science Foundation of China (No.60702027,60921063)the National Basic Research Program of China(973 Program)(No.2010CB327400)the National Science and Technology Major Project of Ministry of Science and Technology of China(No.2010ZX03007-001-01,2011ZX03004-001)
文摘The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.
基金Project supported by the National High-Tech Research and Development Program of China(Nos2008AA010703,2009AA011606)the National Natural Science Foundation of China(No60976023)
文摘A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver（RX）with an ultra-low-power free-running ring oscillator and a high speed main transmitter（TX）with fast lock-in PLL.A passive wake-up receiver（WuRx）for wake-up function with a high power conversion efficiency（PCE）CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm^2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves ＋3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.
基金supported by the National Science & Technology Major Projects of China(No.2009ZX03006-007-01)the National High Technology R&D Program of China(No.2009AA01 Z261)
文摘This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx） cores and a dual-carrier frequency synthesizer（DC-FS） as well as a 3-wire serial peripheral interface（SPI） to set the operating status of the transceiver.The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 x 3.6 mm2.The measurement results show that the wideband Rx achieves an NF of 5-6.2 dB,a max gain of 76-84 dB with 64-dB variable gain,an in-/out-of-band IIP3 of-6/＋4 dBm and an input loss S11 of〈-10 in all bands.The Tx achieves an LOLRR/IMGRR of-34/-33 dBc,a typical OIP3 of＋6 dBm and a maximum output power of -5 dBm.The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of〈1.2 ns.The full chip consumes a maximum current of 420 mA under a 1.2-V supply.
文摘This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.
文摘A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
基金supported by the Zhejian Province Key Subject of C&S Open Funds
文摘This paper presents a 5 GHz CMOS radio frequency （RF） transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple- in multiple-out （MIMO） technology with other wireless technologies to provide high data rate robust real-time high definition television （HDTV） distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz： the industrial, scientific and medical （1SM） band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude （EVM） at -3 dBm output power.
基金Project supported by the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2012BAH20B02)the National Science and Technology Major Projects of the Ministry of Science and Technology of China(No.2012ZX03004007-002)
文摘This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.
