Time synchronization(TS)is crucial for ensuring the secure and reliable functioning of the distribution power Internet of Things(IoT).Multi-clock source time synchronization(MTS)has significant advantages of high reli...Time synchronization(TS)is crucial for ensuring the secure and reliable functioning of the distribution power Internet of Things(IoT).Multi-clock source time synchronization(MTS)has significant advantages of high reliability and accuracy but still faces challenges such as optimization of the multi-clock source selection and the clock source weight calculation at different timescales,and the coupling of synchronization latency jitter and pulse phase difference.In this paper,the multi-timescale MTS model is conducted,and the reinforcement learning(RL)and analytic hierarchy process(AHP)-based multi-timescale MTS algorithm is designed to improve the weighted summation of synchronization latency jitter standard deviation and average pulse phase difference.Specifically,the multi-clock source selection is optimized based on Softmax in the large timescale,and the clock source weight calculation is optimized based on lower confidence bound-assisted AHP in the small timescale.Simulation shows that the proposed algorithm can effectively reduce time synchronization delay standard deviation and average pulse phase difference.展开更多
Power Line Communications-Artificial Intelligence of Things(PLC-AIo T)combines the low cost and high coverage of PLC with the learning ability of Artificial Intelligence(AI)to provide data collection and transmission ...Power Line Communications-Artificial Intelligence of Things(PLC-AIo T)combines the low cost and high coverage of PLC with the learning ability of Artificial Intelligence(AI)to provide data collection and transmission capabilities for PLC-AIo T devices in smart parks.With the development of smart parks,their emerging services require secure and accurate time synchronization of PLC-AIo T devices.However,the impact of attackers on the accuracy of time synchronization cannot be ignored.To solve the aforementioned problems,we propose a tampering attack-aware Deep Q-Network(DQN)-based time synchronization algorithm.First,we construct an abnormal clock source detection model.Then,the abnormal clock source is detected and excluded by comparing the time synchronization information between the device and the gateway.Finally,the proposed algorithm realizes the joint guarantee of high accuracy and low delay for PLC-AIo T in smart parks by intelligently selecting the multi-clock source cooperation strategy and timing weights.Simulation results show that the proposed algorithm has better time synchronization delay and accuracy performance.展开更多
近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-...近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-count rate multi-channel time measurement and serial readout circuit,HMTRC),可实现核事件去稀疏化、去随机化的读出。该电路主要包括了基于时钟分相技术的时间数字转化器、控制器、先进先出存储器和基于令牌环逻辑的轮询读出模块。HMTRC已被集成到一款自研的16通道前端读出ASIC芯片中,可测量和储存时间信息,并利用数字驱动的前端读出架构实现时间与能量信息同步读出。测试表明,时间分辨率好于2 ns,功能符合预期。展开更多
在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自...在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟,并结合ADC的测试模式来确认每一个通道的采样相位,能够自动对每一个通道的延时分别进行调整,以达到对齐各通道采样相位点,保证数据正确采集的目的。最后,基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试,仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位,且最大的采样相位调节范围为±3 bit,信噪比大于65 dB,满足了设计要求和应用需求。展开更多
基金supported by Science and Technology Project of China Southern Power Grid Company Limited under Grant Number 036000KK52200058(GDKJXM20202001).
文摘Time synchronization(TS)is crucial for ensuring the secure and reliable functioning of the distribution power Internet of Things(IoT).Multi-clock source time synchronization(MTS)has significant advantages of high reliability and accuracy but still faces challenges such as optimization of the multi-clock source selection and the clock source weight calculation at different timescales,and the coupling of synchronization latency jitter and pulse phase difference.In this paper,the multi-timescale MTS model is conducted,and the reinforcement learning(RL)and analytic hierarchy process(AHP)-based multi-timescale MTS algorithm is designed to improve the weighted summation of synchronization latency jitter standard deviation and average pulse phase difference.Specifically,the multi-clock source selection is optimized based on Softmax in the large timescale,and the clock source weight calculation is optimized based on lower confidence bound-assisted AHP in the small timescale.Simulation shows that the proposed algorithm can effectively reduce time synchronization delay standard deviation and average pulse phase difference.
基金supported by the Science and Technology Project of the State Grid Corporation of China under Grant Number 5400202199541A-0-5-ZN。
文摘Power Line Communications-Artificial Intelligence of Things(PLC-AIo T)combines the low cost and high coverage of PLC with the learning ability of Artificial Intelligence(AI)to provide data collection and transmission capabilities for PLC-AIo T devices in smart parks.With the development of smart parks,their emerging services require secure and accurate time synchronization of PLC-AIo T devices.However,the impact of attackers on the accuracy of time synchronization cannot be ignored.To solve the aforementioned problems,we propose a tampering attack-aware Deep Q-Network(DQN)-based time synchronization algorithm.First,we construct an abnormal clock source detection model.Then,the abnormal clock source is detected and excluded by comparing the time synchronization information between the device and the gateway.Finally,the proposed algorithm realizes the joint guarantee of high accuracy and low delay for PLC-AIo T in smart parks by intelligently selecting the multi-clock source cooperation strategy and timing weights.Simulation results show that the proposed algorithm has better time synchronization delay and accuracy performance.
文摘近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-count rate multi-channel time measurement and serial readout circuit,HMTRC),可实现核事件去稀疏化、去随机化的读出。该电路主要包括了基于时钟分相技术的时间数字转化器、控制器、先进先出存储器和基于令牌环逻辑的轮询读出模块。HMTRC已被集成到一款自研的16通道前端读出ASIC芯片中,可测量和储存时间信息,并利用数字驱动的前端读出架构实现时间与能量信息同步读出。测试表明,时间分辨率好于2 ns,功能符合预期。
文摘在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟,并结合ADC的测试模式来确认每一个通道的采样相位,能够自动对每一个通道的延时分别进行调整,以达到对齐各通道采样相位点,保证数据正确采集的目的。最后,基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试,仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位,且最大的采样相位调节范围为±3 bit,信噪比大于65 dB,满足了设计要求和应用需求。
