As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is ...As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is constant. The vertically linearly graded concentration drift can be achieved by impurity implanting followed by thermal diffusion. In this way,the vertical breakdown voltage of SOI LDMOS with 2μm thickness SOI layer can be improved by 43%. The on-state resistance is lowered by 24 % because of the higher impurity concentration of the SOI surface.展开更多
To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which i...To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.展开更多
An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire le...An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.展开更多
Based on a ripped-up and rerouted methodology,a multilayer area detailed router is presented by using simulated evolution technique.A modified maze algorithm is also performed for the single net.
文摘As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is constant. The vertically linearly graded concentration drift can be achieved by impurity implanting followed by thermal diffusion. In this way,the vertical breakdown voltage of SOI LDMOS with 2μm thickness SOI layer can be improved by 43%. The on-state resistance is lowered by 24 % because of the higher impurity concentration of the SOI surface.
基金The National Key Project of Scientific and Technical Supporting Programs (No.2006BAK07B04)
文摘To obtain a better placement result, a partitioning-based placement algorithm with wirelength prediction called HJ-Pl is presented. A new method is proposed to estimate proximity of interconnects in a netlist, which is capable of predicting not only short interconnects but long interconnects accurately. The predicted wirelength is embedded into the partitioning tool of bisection-based global placement, which can guide our placement towards a solution with shorter interconnects. In addition, the timing objective can be handled within the algorithm by minimizing the critical path delay. Experimental results show that, compared to Capol0. 5, mPL6, and NTUplace, HJ-P1 outperforms these placers in terms of wirelength and run time. The improvements in terms of average wirelength over Capo10. 5, mPL6 and NPUplace are 13%, 3%, and 9% with only 19%, 91%, and 99% of their runtime, respectively. By integrating the predicted wirelength-driven clustering into Capo10. 5, the placer is able to reduce average wirelength by 3%. The timing-driven HJ-P1 can reduce the critical path delay by 23%.
文摘An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.
文摘Based on a ripped-up and rerouted methodology,a multilayer area detailed router is presented by using simulated evolution technique.A modified maze algorithm is also performed for the single net.
