利用TFC光学膜系设计软件,设计出空间用GaInP/(In)GaAs/Ge三结太阳电池的分布式布拉格反射器(DBR)。由15对Al0.2Ga0.8As/Al0.9Ga0.1As组成的布拉格反射器在中心波长850 nm处反射率高达96%,可以使800~900 nm波段内红外光有效反射后被二...利用TFC光学膜系设计软件,设计出空间用GaInP/(In)GaAs/Ge三结太阳电池的分布式布拉格反射器(DBR)。由15对Al0.2Ga0.8As/Al0.9Ga0.1As组成的布拉格反射器在中心波长850 nm处反射率高达96%,可以使800~900 nm波段内红外光有效反射后被二次吸收,提高了Ga As子电池的抗辐照能力。通过对两种电池结构A、B地面模拟辐照试验获得1 Me V电子辐照下Ga In P/Ga As/Ge太阳电池电学参数随辐照注量退化的基本规律。在此基础上应用PC1D模拟程序分析太阳电池内部的载流子输运机理,建立1 Me V电子辐照下两种电池结构中多数载流子浓度和少数载流子扩散长度随辐照电子注量变化的基本规律。研究结果表明,多数载流子浓度和少数载流子扩散长度均随入射电子注量的增大而减小,同时原电池结构A中多数载流子去除率和少数载流子扩散长度损伤系数明显高于新电池结构B,由此表明包含布拉格反射器的新电池结构具有更强的抗辐照能力。展开更多
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challen...This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.展开更多
文摘利用TFC光学膜系设计软件,设计出空间用GaInP/(In)GaAs/Ge三结太阳电池的分布式布拉格反射器(DBR)。由15对Al0.2Ga0.8As/Al0.9Ga0.1As组成的布拉格反射器在中心波长850 nm处反射率高达96%,可以使800~900 nm波段内红外光有效反射后被二次吸收,提高了Ga As子电池的抗辐照能力。通过对两种电池结构A、B地面模拟辐照试验获得1 Me V电子辐照下Ga In P/Ga As/Ge太阳电池电学参数随辐照注量退化的基本规律。在此基础上应用PC1D模拟程序分析太阳电池内部的载流子输运机理,建立1 Me V电子辐照下两种电池结构中多数载流子浓度和少数载流子扩散长度随辐照电子注量变化的基本规律。研究结果表明,多数载流子浓度和少数载流子扩散长度均随入射电子注量的增大而减小,同时原电池结构A中多数载流子去除率和少数载流子扩散长度损伤系数明显高于新电池结构B,由此表明包含布拉格反射器的新电池结构具有更强的抗辐照能力。
文摘This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
