The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of ...The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor （FET） based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 }_ts. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive （RC） delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.展开更多
基金This work was supported by the National Basic Research Program of China （Nos. 2011CB933001 and 2011CB933002）, the National Natural Science Foundation of China （Nos. 61322105, 61271051, 61376126, 61321001 and 61390504）, and the Beijing Municipal Science and Technology Commission （Nos. Z131100003213021 and 20121000102）.
文摘The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor （FET） based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 }_ts. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive （RC） delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.
