A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated...A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.展开更多
As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed ...As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics.In this paper,we propose a layout method called Maximum Operating Frequency Constraint(MOFC)for SFQ circuit design.Using this method,we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology,which holds practical value.The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits,contributing to less energy consumption.To the best of our knowledge,this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing.Our chip has been fabricated and tested,revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.展开更多
Rapid single flux quantum(RSFQ)circuits have the advantages of high speed and low power consumption.The typical frequency of the RSFQ circuits is tens of GHz.Therefore,it is necessary to reliably test the highfrequenc...Rapid single flux quantum(RSFQ)circuits have the advantages of high speed and low power consumption.The typical frequency of the RSFQ circuits is tens of GHz.Therefore,it is necessary to reliably test the highfrequency performance of RSFQ circuits simply and effectively.This paper proposes a new on-chip highfrequency testing method,which uses pseudo-random sequences generated by linear feedback shift register(LFSR)as the test vectors,and the output shift registers(SRs)to store the last piece of high-frequency testing result and read out it at low-frequency.Unlike the traditional high-frequency demonstration method of using the Input/Output SRs,our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost,making the whole high-frequency demonstration more reliable and convincing.On the other hand,this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits.This work verified the proposed method,and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.展开更多
基金supported by the National Key Research and Development Program of China(Grant No.2017YFA0304003)。
文摘A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.
文摘As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics.In this paper,we propose a layout method called Maximum Operating Frequency Constraint(MOFC)for SFQ circuit design.Using this method,we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology,which holds practical value.The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits,contributing to less energy consumption.To the best of our knowledge,this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing.Our chip has been fabricated and tested,revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.
基金supported by the National Natural Science Foundation of China under Grant No.92164101the National Natural Science Foundation of China under Grant No.62171437+2 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDA18000000Shanghai Science and Technology Committee(Grant No.21DZ1101000)the National Key R&D Program of China under Grant No.2021YFB0300400.
文摘Rapid single flux quantum(RSFQ)circuits have the advantages of high speed and low power consumption.The typical frequency of the RSFQ circuits is tens of GHz.Therefore,it is necessary to reliably test the highfrequency performance of RSFQ circuits simply and effectively.This paper proposes a new on-chip highfrequency testing method,which uses pseudo-random sequences generated by linear feedback shift register(LFSR)as the test vectors,and the output shift registers(SRs)to store the last piece of high-frequency testing result and read out it at low-frequency.Unlike the traditional high-frequency demonstration method of using the Input/Output SRs,our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost,making the whole high-frequency demonstration more reliable and convincing.On the other hand,this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits.This work verified the proposed method,and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.
