研究并设计了一种应用于全球数字广播(Digital Radio Mondiale,DRM/DRM+)接收机射频芯片系统结构,设计了相关模块和电路,包括一种高灵敏度有限空间内中短波宽带接收天线、基于噪声抵消和跨导线性技术的DRM第一中频下变频模块、带输出分...研究并设计了一种应用于全球数字广播(Digital Radio Mondiale,DRM/DRM+)接收机射频芯片系统结构,设计了相关模块和电路,包括一种高灵敏度有限空间内中短波宽带接收天线、基于噪声抵消和跨导线性技术的DRM第一中频下变频模块、带输出分频器的吞除脉冲式的频率综合器、DRM双正交镜像抑制混频器、中频可变增益放大器以及中频计数器模块等。芯片模块采用中芯国际(SMIC)0.18μm RF CMOS工艺实现,测试结果表明能够满足DRM接收机系统要求。展开更多
The design of low-power LVDS（low voltage differential signaling） transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is p...The design of low-power LVDS（low voltage differential signaling） transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports the failsafe function.The transceiver chips were verified with the CSMC 0.5-μm CMOS process.The measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/s.The power consumption is 6 mA with a 5-V power supply.The LVDS receiver can work properly with a larger input common mode voltage（0.1-2.4 V） but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s.The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.展开更多
文摘研究并设计了一种应用于全球数字广播(Digital Radio Mondiale,DRM/DRM+)接收机射频芯片系统结构,设计了相关模块和电路,包括一种高灵敏度有限空间内中短波宽带接收天线、基于噪声抵消和跨导线性技术的DRM第一中频下变频模块、带输出分频器的吞除脉冲式的频率综合器、DRM双正交镜像抑制混频器、中频可变增益放大器以及中频计数器模块等。芯片模块采用中芯国际(SMIC)0.18μm RF CMOS工艺实现,测试结果表明能够满足DRM接收机系统要求。
文摘The design of low-power LVDS（low voltage differential signaling） transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports the failsafe function.The transceiver chips were verified with the CSMC 0.5-μm CMOS process.The measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/s.The power consumption is 6 mA with a 5-V power supply.The LVDS receiver can work properly with a larger input common mode voltage（0.1-2.4 V） but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s.The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.
