This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13μm CMOS technology.The frequency synthesizer is implemented with an on-chip symmetric inductor...This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13μm CMOS technology.The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter.A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration.Pulse-swallow topology with a multistage noise shaping△Σmodulator is adopted in the frequency divider design.The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes.Measurement results show that the phase noise of the synthesizer achieves -91.3 dBc/Hz and -117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset,separately.The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm;.展开更多
A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled osci...A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled oscillator（VCO） is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping（MASH）△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector （PFD） frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm^2.展开更多
A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is inte...A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.展开更多
A fully integrated △∑ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network （WLAN） transceivers. A low noise filter...A fully integrated △∑ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network （WLAN） transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm^2excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.展开更多
A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based techniqu...A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.展开更多
An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th orde...An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th order elliptic lowpass filters（LPFs）,transmitter（TX） 3rd order Chebyshev LPFs,RX programmable gain amplifiers （PGAs） with DC offset cancellation（DCOC） servo loops,and on-chip output buffers.The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/（Hz）^（1/2） input referred noise（IRN） and a 21 to -41 dBm in-band 3rd order interception point（IIP3）.The RX/TX LPF cutoff frequencies can be switched between 5 MHz,10 MHz,and 20 MHz to fulfill the multimode 802.11b/g/n requirements.The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX 1/Q gain mismatches.By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array,the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.展开更多
文摘This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13μm CMOS technology.The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter.A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration.Pulse-swallow topology with a multistage noise shaping△Σmodulator is adopted in the frequency divider design.The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes.Measurement results show that the phase noise of the synthesizer achieves -91.3 dBc/Hz and -117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset,separately.The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm;.
文摘A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled oscillator（VCO） is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping（MASH）△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector （PFD） frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm^2.
文摘A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.
文摘A fully integrated △∑ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network （WLAN） transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm^2excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.
文摘A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.
文摘An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th order elliptic lowpass filters（LPFs）,transmitter（TX） 3rd order Chebyshev LPFs,RX programmable gain amplifiers （PGAs） with DC offset cancellation（DCOC） servo loops,and on-chip output buffers.The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/（Hz）^（1/2） input referred noise（IRN） and a 21 to -41 dBm in-band 3rd order interception point（IIP3）.The RX/TX LPF cutoff frequencies can be switched between 5 MHz,10 MHz,and 20 MHz to fulfill the multimode 802.11b/g/n requirements.The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX 1/Q gain mismatches.By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array,the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.
