This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence ...This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
An inductorless Ultra-Wide Band （UWB） receiver frontend chip design used in wireless communications for the frequency band of 3.1 - 4.8 GHz is presented. This ho-nodyne receiver mainly consists of a diffexential Low...An inductorless Ultra-Wide Band （UWB） receiver frontend chip design used in wireless communications for the frequency band of 3.1 - 4.8 GHz is presented. This ho-nodyne receiver mainly consists of a diffexential Low Noise Amplifier （LNA） circuit followed by a down-converting mixer. The proposed LNA circuit with a noise canceling resistor is connected to the CMOS device＇s body to reduce the substrate thermal noise. Simulation and measuremnt results show that the chip can reduce the froat-end Noise Figure （NF） about 0.5dB and achieve the Conversion Gain （03） of 19.44-21.57 dB and double-sideband NF less than 7.8 dB. Also, the input third-order interoept point （IIP3） is - 11 dBm, and the input second-order intercept point （IIP2） is 49 dBm. Fabricated in TSMC 0.18 tan technology, this chip occupies only 0. 167 Iron2 and dissipates power 59.2 roW.展开更多
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
文摘This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
文摘An inductorless Ultra-Wide Band （UWB） receiver frontend chip design used in wireless communications for the frequency band of 3.1 - 4.8 GHz is presented. This ho-nodyne receiver mainly consists of a diffexential Low Noise Amplifier （LNA） circuit followed by a down-converting mixer. The proposed LNA circuit with a noise canceling resistor is connected to the CMOS device＇s body to reduce the substrate thermal noise. Simulation and measuremnt results show that the chip can reduce the froat-end Noise Figure （NF） about 0.5dB and achieve the Conversion Gain （03） of 19.44-21.57 dB and double-sideband NF less than 7.8 dB. Also, the input third-order interoept point （IIP3） is - 11 dBm, and the input second-order intercept point （IIP2） is 49 dBm. Fabricated in TSMC 0.18 tan technology, this chip occupies only 0. 167 Iron2 and dissipates power 59.2 roW.
